Stress is a constant presence in the semiconductors manufacturing. It can cause wafers to become warped and less manageable, and in worst cases it can even cause breakage of wafers.
Methods of reducing thermal stress are disclosed in the prior art.
JP 02-181425 discloses plural sets of pinhole shaped through holes, which are made in advance. These holes are formed in scribe lanes on the wafer. Thereto an etch process is used.
However, an etch process, such as a RIE process, provides for a speed of 1 to 10 μm per minute, on a wafer that typically is 300 to 400 μm thick. Therefore the cost involved is quite high, especially in view of the small number of holes that are formed.
Clearly the time involved for etching is quite long, which makes the process unfavorable, also in terms of costs allocated to use of equipment, chemicals, and environmental and health risks. Furthermore, even wafers comprising plural sets of through holes suffer from warpage, albeit at a lower extend.
JP 2002-134451 discloses grooves that are formed on dicing streets used in an assembly process by etching in a plasma treatment, in order to reduce warpage before the grinding process.
This clearly means that all process steps before that final operation, i.e. grinding, including wafer test, have been done on a potentially warped wafer. Further, performing a plasma treatment on a finished wafer, if not perfectly controlled, could damage adjacent sensitive structures on the integrated circuits
US2001/0014515 discloses a method of preparing a semiconductor wafer, including the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Herein, rectangular grooves running over the length of a wafer are formed, or separate grooves in at least one of the scribe lanes, which are processed with specific mask layers and patterning within scribe lines. The depth of the grooves is claimed to help reduce the possibility that the grooves are buried during the formation of the integrated circuit devices. The depth of the grooves is preferably greater than total thickness of the layers deposited.
US2003/0216009A1 discloses a method for preventing warpage of wafers, wherein grooves for attenuating warp are formed in scribe regions, except in the scribe regions such that the alignment pattern forming regions remain in the scribe region.
Thus, grooves are formed, which are continuous. A disadvantage hereof is that the necessity to interrupt grooves in the alignment pattern regions exists. Further, stress reduction is less effective when a groove does not run all over the wafer.
US2005/0194670A1 discloses a method for preventing warpage of wafers, wherein a glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface.
This method is regarded as being expensive and rather complicated.
Thus there still is a need for a method for preventing warpage on a wafer which is simple, efficient in terms of process time, the amount of chemicals used, which should not involve extra process steps, which is environmental friendly, and relatively safe.